The VDMOS model as used in LTspice simulator can model power MOSFET's nicely.

I have extracted parameters for the IRF640 (aka IRFP240) and IRF9640 (aka IRFP9240) from the Vishay datasheet and have written a PDF showing each step so you can do the same for your own MOSFET's.

You can download several software jig's to help in the process. All downloads here are free under Creative Commons 4 Attribution, no liability accepted. Please let me know if you find errors (use the Contact tab).

I also extracted the Exicon 10N20, 10P20 and 20N20 ,20P20 lateral MOSFET's from datasheets as well as from actual accurate pulse tester measurements. The jig data is available in a spreadsheet. The pulse tester jig has a PDF on how it works, and it's not hard to make one.

There is also a PDF on a subcircuit that adds quasisaturation to the VDMOS. The files are also provided free for downloading.

LTspice files below for the 'VDMOS parameter extraction' paper (see PDF downloads):

1. Download "Compare Extractions.asc" LTspice jig here
2. Download "Plot gate charge.asc" jig here 
3. Download "Plot Cds.asc" jig here 
4. Download "Plot body diode.asc" jig here 

LTspice files below for the 'Simple pulse jig for power MOSFETs' paper (see PDF downloads):

1. Download "VDMOS+EKV-10x20+20x20" LTspice jigs and Spreadsheet here

LTspice files below for the 'Subcircuit to add quasisaturation' paper (see PDF downloads):

1. Download "VDMOS-4049-QuasiSat" LTspice jig here

Download "VDMOS-internal-Temp-co-jig" here